The field-effect transistor (FET) uses the effects of an electric field to turn the current flow through the transistor on and off. Two principal FET configurations exist. The first is a semiconductor device with an NMOS configuration having an n-channel in a p-well. The second is a semiconductor device with a PMOS configuration having a p-channel in an n-well. A CMOS configuration simply pairs together an NMOS and a PMOS transistor. The principles below are applicable to both types of devices.
The transistor has two terminals that are referred to as a drain and a source. The terminals are separated by a channel region over which a gate resides. A thin layer of dielectric material, called gate oxide, separates the gate electrode from the wells. The electric field created from a relative voltage V.sub.GS, between the gate and the source terminal either enhances or depletes the carriers in the channel region below the gate, depending on the type of device and the gate voltage. The presence or lack of these carriers directly controls the current flow (from zero to maximum amperage current) between the two terminals. The voltage, V.sub.GS, at which a conducting channel is formed, i.e. the device turns on, is called the threshold voltage, V.sub.T.
Doping the well and the channel region with impurities has a significant affect on the performance of the transistor and, for example, how and when it turns on and off. The channel region below the gate is doped with impurities having carriers that affect the current carrying capabilities.
The carrier-type of the impurity used in these locations depends on whether the semiconductor is designed as an enhancement or depletion type device. An enhancement device uses carriers in the channel opposite of those in the wells. It is the difference in carriers that prevents current flow from occurring at zero bias, V.sub.GS =0 and that allow current flow at a positive bias, V.sub.GS &gt;0.
In contrast, a depletion device uses carriers in the channel that are the same as those used in the well. Because the carriers are the same, current flow occurs at zero bias between the gate and drain. Similarly, current flow is prevented at a negative bias, V.sub.GS &lt;0. Hence, the threshold voltage in a depletion device is negative.
Doping the channel region affects the V.sub.T characteristics. The prior art requires the channel region to be doped with an impurity-concentration that yields an acceptable V.sub.T. A low V.sub.T allows leakage current through the device at the low turn-off voltage while a high V.sub.T prevents leakage current at the low turn-off voltage.
The following items refer to the performance of a transistor in the sub-threshold region. The sub-threshold region refers to the performance of the device at voltages below V.sub.T. Literally, this is the region where the device is turning-off, i.e. the current through the device approaches zero. How well the device approaches zero current defines the heating and power loss due to leakage current through the device.
Referring now to Prior Art FIG. 1, a graph showing the Logarithm of I.sub.ds, current vs. V.sub.GS voltage for a depletion device is presented. The initial slope 100 (in units of decade amps/mV) of the curve 102 represents how well or how quickly the current shuts off as the bias voltage to the gate changes. The inverse of this slope is called the S-factor (in units of mV/decade amps). The theoretical minimum s-factor is 60 mV/ decade amps. As a benchmark, the S-factor defines how well the device turns on and off. It is desirable to have a steep S-factor for acceptable gate swing, or switching, properties. The prior art has a typical middle slope 102 value of 80-90 mV/decade amps.
The S-factor is directly proportional to the dopant concentration in the channel. For example, an increase in concentration decreases the slope. Explained another way, a higher concentration of dopant in the channel region means that a greater voltage will have to be applied to change the state of the device from on to off. Curve 104 represents a theoretical curve that the prior art desires to reach but is currently not feasible.
Focusing now on Prior Art FIG. 2, a graph showing Logarithm of Dopant concentration vs. Distance in the semiconductor substrate is presented. This graph represents the high dopant-concentration profile needed by the prior art to obtain the switching properties referred to in the previous paragraph. The curve is referred to as the standard-profile doping curve (ST-profile). Theoretically, the ideal curve 200 is desired, but in reality, only the actual curve 202 is obtainable.
Prior Art FIG. 3 is an illustration of the Electron-Dopant Scattering Interference. The Electron-Dopant interference occurs when a high concentration of dopant 300 is present in the channel-region 302 of the substrate. The high concentration of dopant is required to set the threshold voltage, V.sub.T, at a reasonably high level to prevent leakage at turn-off voltage. Thus, when voltage between the two terminals increases, providing an electromotive force to drive current across the channel, the current rises until it reaches saturation. Decreased carrier mobility and scattering is responsible for setting the saturation level. Unfortunately, when the dopant is in sufficiently high concentrations, it acts as a physical interference to the electrons 304 in the current stream flowing through the channel region 302 of the substrate, as electrons in the current stream are scattered and cannot efficiently flow across the channel. Hence, the maximum amount of current the channel can carry, I.sub.dsat is limited. The low current capability I.sub.dsat in the prior art is a serious limitation on semiconductor devices.
Complicating these limitations in the prior art is the fact that nMOSFET devices are approaching a channel length near the 0.1 micrometer range. For devices this small to be effective, a very thin gate oxide and a very high channel doping concentration is required. These features cause severe performance degradation due to impurity scattering and highly-impeded carrier mobility in the high transverse electric fields at the Silicon/Silicon-dioxide interface. These large transverse electric fields lead to quantum mechanical (QM) effects that reduce the inversion layer charge density at a given gate voltage. Hence, the magnitude of the threshold voltage V.sub.T increases. The overall impact of QM effects is the degradation of device performance. Due to these characteristics, conventional scaling of MOSFET devices to the desired smaller size is ineffective.
Thus, a need exists for a semiconductor device and formation method which provides a sufficient channel-region doping concentration such that a reduced threshold voltage can be used to achieve a desired current flow. Still another need exists for a semiconductor device and formation method that meets the above two needs but does not suffer unreasonable leakage current in the shut-off mode. A further need exists for a semiconductor device and formation method that meets the above need but that also does not suffer from highly-impeded carrier mobility. Finally, a need exists for a device with improved subthreshold swing that will enable faster device switching from the on-state to the off-state and vice versa.